(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having polysilicon plugs and, more particularly, to a heat treatment technique after forming polysilicon plugs in a semiconductor device.
(b) Description of the Related Art
A DRAM (dynamic random access memory) device includes therein a memory cell area for storing data and a peripheral circuit area for controlling write/read of data into/from the memory cell area. Each DRAM memory cell in the memory cell area includes a capacitor for storing therein electric charge and a cell transistor acting as a switch for supplying the electric charge to the capacitor. A cell transistor may include a polysilicon electrode, or polysilicon plug, in contact with a diffused region of the cell transistor.
FIGS. 2A to 2F consecutively show a conventional fabrication process for manufacturing a DRAM device. First, as shown in FIG. 2A, an isolation region 12, known as a shallow isolation trench, is formed on a surface region of a silicon substrate 11 by using a known technique, for isolating a memory cell area 10A from a peripheral circuit area 10B.
Subsequently, an ion-implantation step is conducted for forming an n-type shield layer 13 in a deep region of the silicon substrate 11. Then, a p-type well layer (p-well) 14 is formed on the n-type shield layer 13 in the memory-cell transistor area 10A, whereas an n-type well layer (n-well) 15 is formed on the n-type shield layer 13 in the peripheral circuit area 10B. Thereafter, a p-type channel layer and an n-type channel layer are formed on the p-well 14 and n-well 15, respectively, although these channel layers are not specifically shown in FIG. 2A.
Subsequently, a gate oxide film 16 is formed on the entire area of the silicon substrate 11 by using a thermal oxidation technique, followed by depositing a gate electrode layer on the gate oxide film 16 by sputtering. A patterned insulation film 18 is then used for patterning the deposited gate electrode layer to thereby form gate electrodes 17, to obtain the structure shown in FIG. 2A.
Thereafter, phosphorous is implanted into the memory cell area 10A by ion-implantation using the patterned insulation film 18 as a mask to form lightly-doped diffused regions 19, whereas boron is implanted into the peripheral circuit area 10B by ion-implantation using the patterned insulation film 18 as a mask to form lightly-doped diffused regions 20. A heat treatment is then performed to activate the implanted phosphorous in the n-type lightly-doped diffused regions 19 and the implanted boron in the p-type lightly-doped diffused regions 20, to thereby obtain the structure shown in FIG. 2B.
Subsequently, side spacers 21 are formed on the side walls of the gate electrodes 17 and the overlying patterned insulation film 18 by using a known technique. Boron is again implanted into the peripheral circuit area 10B by using the patterned insulation film 18 and the side spacers 21 as a mask, followed by a heat treatment to activate the implanted boron to form p-type heavily-doped diffused regions 22 in the peripheral circuit area 10B, as shown in FIG. 2C.
Thereafter, a first interlevel dielectric film 23 is deposited on the entire surface, followed by forming through-holes 26 in the first interlevel dielectric film 23 within the memory cell area 10A to reach the n-type diffused regions 19. Phosphorous is then implanted into the regions underlying the n-type diffused regions 19 by using the first interlevel dielectric film 23 and the side spacers 21 as a mask in the memory cell area 10A. This phosphorous implantation is performed to form electric-field alleviation regions underlying the n-type diffused regions 19. Polysilicon contact plugs 24 are then formed to fill the through-holes 26, as shown in FIG. 2D.
A second interlevel dielectric film 25 is then deposited on the entire area, as shown in FIG. 2E, followed by a high-temperature heat treatment in a N2 environment at a temperature of 1,000 degrees C. for 10 seconds. This high-temperature heat treatment reduces the resistances of the polysilicon plugs 24 as well as the contact resistances between the contact plugs 24 and the n-type diffused regions 19.
Through-holes 27 are then formed in the second interlevel dielectric film 25 within the memory cell area 10A to reach the polysilicon plugs 24. Through-holes 28 are then formed in the first and second interlevel dielectric films 23 and 25 within the peripheral circuit area 10B to reach the p-type heavily-doped diffused regions 22. Thereafter, thin titanium film, thin titanium nitride film and tungsten film are consecutively deposited to obtain a layered metallic film. A heat treatment is then conducted at a temperature of about 700 degrees C. for around 10 minutes to react the titanium in the titanium film with the silicon substrate 11 to form titanium silicide film, which achieves an excellent contact resistance between the layered metallic film and the p-type diffused region 22.
Thereafter, the layered metallic film is subjected to patterning to form metallic plugs 29 in contact with the polysilicon plugs 24 within the memory cell area 10A and metallic plugs 30 in contact with the p-type heavily-doped diffused regions 22 within the peripheral circuit area 10B. Thereafter, a variety of known steps are performed such as forming capacitors connected to polysilicon plugs 24 within the memory cell area 10A, thereby completing a DRAM device 10.
In the conventional DRAM device as described above, the structure wherein the metallic plugs in contact with the diffused regions are used in the peripheral-circuit-area 10B is employed because metallic silicide achieving an excellent lower resistance is formed between the metallic plugs and the diffused regions by using the heat treatment. This structure is not used in the memory cell area 10A however, because there is a possibility that junction leakage current is increased because the metallic atoms such as titanium and cobalt are diffused within the silicon substrate to form recombination centers. That is, polysilicon plugs in contact with the diffused regions are used in the memory cell area 10A to suppress occurrence of the junction leakage current and thereby achieve a longer data retention time in the memory cell. The method for manufacturing a DRAM device wherein polysilicon plugs and metallic plugs are in contact with diffused regions is described in Patent Publication JP-A-2003-31684.
In order to improve the characteristics of the DRAM device, it is essential to suppress the junction leakage current of the cell transistor as well as to reduce the contact resistances between the contact plugs and the diffused regions. However, conventional methods for manufacturing a DRAM device have respective drawbacks and cannot achieve both a reduced junction leakage current and a lower contact resistance in the memory cell.